/*
 * Copyright (C) 2019 Unigroup Spreadtrum & RDA Technologies Co., Ltd.
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 * updated at 2019-01-07 15:09:47
 *
 */


#ifndef ANLG_PHY_G3_H
#define ANLG_PHY_G3_H

#define CTL_BASE_ANLG_PHY_G3 0x30050000


#define REG_ANLG_PHY_G3_ANALOG_DPLL_TOP_DPLL0_CTRL0          ( CTL_BASE_ANLG_PHY_G3 + 0x0000 )
#define REG_ANLG_PHY_G3_ANALOG_DPLL_TOP_DPLL0_CTRL1          ( CTL_BASE_ANLG_PHY_G3 + 0x0004 )
#define REG_ANLG_PHY_G3_ANALOG_DPLL_TOP_DPLL0_CTRL2          ( CTL_BASE_ANLG_PHY_G3 + 0x0008 )
#define REG_ANLG_PHY_G3_ANALOG_DPLL_TOP_DPLL0_BIST_CTRL      ( CTL_BASE_ANLG_PHY_G3 + 0x000C )
#define REG_ANLG_PHY_G3_ANALOG_DPLL_TOP_ANA_DPLL0_DUMY       ( CTL_BASE_ANLG_PHY_G3 + 0x0010 )
#define REG_ANLG_PHY_G3_ANALOG_DPLL_TOP_DPLL1_CTRL0          ( CTL_BASE_ANLG_PHY_G3 + 0x0014 )
#define REG_ANLG_PHY_G3_ANALOG_DPLL_TOP_DPLL1_CTRL1          ( CTL_BASE_ANLG_PHY_G3 + 0x0018 )
#define REG_ANLG_PHY_G3_ANALOG_DPLL_TOP_DPLL1_CTRL2          ( CTL_BASE_ANLG_PHY_G3 + 0x001C )
#define REG_ANLG_PHY_G3_ANALOG_DPLL_TOP_DPLL1_BIST_CTRL      ( CTL_BASE_ANLG_PHY_G3 + 0x0020 )
#define REG_ANLG_PHY_G3_ANALOG_DPLL_TOP_DPLL_FREQ_CTRL       ( CTL_BASE_ANLG_PHY_G3 + 0x0024 )
#define REG_ANLG_PHY_G3_ANALOG_DPLL_TOP_ANA_DPLL1_DUMY       ( CTL_BASE_ANLG_PHY_G3 + 0x0028 )
#define REG_ANLG_PHY_G3_ANALOG_DPLL_TOP_REG_SEL_CFG_0        ( CTL_BASE_ANLG_PHY_G3 + 0x002C )

/* REG_ANLG_PHY_G3_ANALOG_DPLL_TOP_DPLL0_CTRL0 */

#define BIT_ANLG_PHY_G3_ANALOG_DPLL_TOP_DPLL0_N(x)                (((x) & 0x7FF) << 18)
#define BIT_ANLG_PHY_G3_ANALOG_DPLL_TOP_DPLL0_IBIAS(x)            (((x) & 0x3) << 16)
#define BIT_ANLG_PHY_G3_ANALOG_DPLL_TOP_DPLL0_LPF(x)              (((x) & 0x7) << 13)
#define BIT_ANLG_PHY_G3_ANALOG_DPLL_TOP_DPLL0_SDM_EN              BIT(12)
#define BIT_ANLG_PHY_G3_ANALOG_DPLL_TOP_DPLL0_MOD_EN              BIT(11)
#define BIT_ANLG_PHY_G3_ANALOG_DPLL_TOP_DPLL0_DIV_S               BIT(10)
#define BIT_ANLG_PHY_G3_ANALOG_DPLL_TOP_DPLL0_RESERVED(x)         (((x) & 0xFF) << 2)
#define BIT_ANLG_PHY_G3_ANALOG_DPLL_TOP_DPLL0_CLKOUT_EN           BIT(1)
#define BIT_ANLG_PHY_G3_ANALOG_DPLL_TOP_DPLL0_LOCK_DONE           BIT(0)

/* REG_ANLG_PHY_G3_ANALOG_DPLL_TOP_DPLL0_CTRL1 */

#define BIT_ANLG_PHY_G3_ANALOG_DPLL_TOP_DPLL0_PD                  BIT(31)
#define BIT_ANLG_PHY_G3_ANALOG_DPLL_TOP_DPLL0_RST                 BIT(30)
#define BIT_ANLG_PHY_G3_ANALOG_DPLL_TOP_DPLL0_NINT(x)             (((x) & 0x7F) << 23)
#define BIT_ANLG_PHY_G3_ANALOG_DPLL_TOP_DPLL0_KINT(x)             (((x) & 0x7FFFFF))

/* REG_ANLG_PHY_G3_ANALOG_DPLL_TOP_DPLL0_CTRL2 */

#define BIT_ANLG_PHY_G3_ANALOG_DPLL_TOP_DPLL0_DIV_SEL(x)          (((x) & 0xF) << 8)
#define BIT_ANLG_PHY_G3_ANALOG_DPLL_TOP_DPLL0_CCS_CTRL(x)         (((x) & 0xFF))

/* REG_ANLG_PHY_G3_ANALOG_DPLL_TOP_DPLL0_BIST_CTRL */

#define BIT_ANLG_PHY_G3_ANALOG_DPLL_TOP_DPLL0_BIST_EN             BIT(16)
#define BIT_ANLG_PHY_G3_ANALOG_DPLL_TOP_DPLL0_BIST_CNT(x)         (((x) & 0xFFFF))

/* REG_ANLG_PHY_G3_ANALOG_DPLL_TOP_ANA_DPLL0_DUMY */

#define BIT_ANLG_PHY_G3_ANALOG_DPLL_TOP_ANALOG_DPLL0_DUMY_IN(x)   (((x) & 0xFFFF) << 16)
#define BIT_ANLG_PHY_G3_ANALOG_DPLL_TOP_ANALOG_DPLL0_DUMY_OUT(x)  (((x) & 0xFFFF))

/* REG_ANLG_PHY_G3_ANALOG_DPLL_TOP_DPLL1_CTRL0 */

#define BIT_ANLG_PHY_G3_ANALOG_DPLL_TOP_DPLL1_N(x)                (((x) & 0x7FF) << 18)
#define BIT_ANLG_PHY_G3_ANALOG_DPLL_TOP_DPLL1_IBIAS(x)            (((x) & 0x3) << 16)
#define BIT_ANLG_PHY_G3_ANALOG_DPLL_TOP_DPLL1_LPF(x)              (((x) & 0x7) << 13)
#define BIT_ANLG_PHY_G3_ANALOG_DPLL_TOP_DPLL1_SDM_EN              BIT(12)
#define BIT_ANLG_PHY_G3_ANALOG_DPLL_TOP_DPLL1_MOD_EN              BIT(11)
#define BIT_ANLG_PHY_G3_ANALOG_DPLL_TOP_DPLL1_DIV_S               BIT(10)
#define BIT_ANLG_PHY_G3_ANALOG_DPLL_TOP_DPLL1_RESERVED(x)         (((x) & 0xFF) << 2)
#define BIT_ANLG_PHY_G3_ANALOG_DPLL_TOP_DPLL1_CLKOUT_EN           BIT(1)
#define BIT_ANLG_PHY_G3_ANALOG_DPLL_TOP_DPLL1_LOCK_DONE           BIT(0)

/* REG_ANLG_PHY_G3_ANALOG_DPLL_TOP_DPLL1_CTRL1 */

#define BIT_ANLG_PHY_G3_ANALOG_DPLL_TOP_DPLL1_PD                  BIT(31)
#define BIT_ANLG_PHY_G3_ANALOG_DPLL_TOP_DPLL1_RST                 BIT(30)
#define BIT_ANLG_PHY_G3_ANALOG_DPLL_TOP_DPLL1_NINT(x)             (((x) & 0x7F) << 23)
#define BIT_ANLG_PHY_G3_ANALOG_DPLL_TOP_DPLL1_KINT(x)             (((x) & 0x7FFFFF))

/* REG_ANLG_PHY_G3_ANALOG_DPLL_TOP_DPLL1_CTRL2 */

#define BIT_ANLG_PHY_G3_ANALOG_DPLL_TOP_DPLL1_DIV_SEL(x)          (((x) & 0xF) << 8)
#define BIT_ANLG_PHY_G3_ANALOG_DPLL_TOP_DPLL1_CCS_CTRL(x)         (((x) & 0xFF))

/* REG_ANLG_PHY_G3_ANALOG_DPLL_TOP_DPLL1_BIST_CTRL */

#define BIT_ANLG_PHY_G3_ANALOG_DPLL_TOP_DPLL1_BIST_EN             BIT(16)
#define BIT_ANLG_PHY_G3_ANALOG_DPLL_TOP_DPLL1_BIST_CNT(x)         (((x) & 0xFFFF))

/* REG_ANLG_PHY_G3_ANALOG_DPLL_TOP_DPLL_FREQ_CTRL */

#define BIT_ANLG_PHY_G3_ANALOG_DPLL_TOP_DPLL0_BAND                BIT(3)
#define BIT_ANLG_PHY_G3_ANALOG_DPLL_TOP_DPLL0_IL_DIV              BIT(2)
#define BIT_ANLG_PHY_G3_ANALOG_DPLL_TOP_DPLL1_BAND                BIT(1)
#define BIT_ANLG_PHY_G3_ANALOG_DPLL_TOP_DPLL1_IL_DIV              BIT(0)

/* REG_ANLG_PHY_G3_ANALOG_DPLL_TOP_ANA_DPLL1_DUMY */

#define BIT_ANLG_PHY_G3_ANALOG_DPLL_TOP_ANALOG_DPLL1_DUMY_IN(x)   (((x) & 0xFFFF) << 16)
#define BIT_ANLG_PHY_G3_ANALOG_DPLL_TOP_ANALOG_DPLL1_DUMY_OUT(x)  (((x) & 0xFFFF))

/* REG_ANLG_PHY_G3_ANALOG_DPLL_TOP_REG_SEL_CFG_0 */

#define BIT_ANLG_PHY_G3_DBG_SEL_ANALOG_DPLL_TOP_DPLL0_CLKOUT_EN   BIT(7)
#define BIT_ANLG_PHY_G3_DBG_SEL_ANALOG_DPLL_TOP_DPLL0_PD          BIT(6)
#define BIT_ANLG_PHY_G3_DBG_SEL_ANALOG_DPLL_TOP_DPLL0_RST         BIT(5)
#define BIT_ANLG_PHY_G3_DBG_SEL_ANALOG_DPLL_TOP_DPLL0_DIV_SEL     BIT(4)
#define BIT_ANLG_PHY_G3_DBG_SEL_ANALOG_DPLL_TOP_DPLL1_CLKOUT_EN   BIT(3)
#define BIT_ANLG_PHY_G3_DBG_SEL_ANALOG_DPLL_TOP_DPLL1_PD          BIT(2)
#define BIT_ANLG_PHY_G3_DBG_SEL_ANALOG_DPLL_TOP_DPLL1_RST         BIT(1)
#define BIT_ANLG_PHY_G3_DBG_SEL_ANALOG_DPLL_TOP_DPLL1_DIV_SEL     BIT(0)


#endif /* ANLG_PHY_G3_H */


